Applications
Receiver Testing (Jitter Tolerance)
The most efficient way to characterize your receiver's performance is to run a jitter tolerance (JTOL) test on all lanes simultaneously. Centellax provides the only affordable solution for testing JTOL in multi-lane applications. Our unique system incorporates a Parallel Channel BERT, a Stressed Clock Source, and remote mountable Error Detector and Pattern Generator Heads so you can customize the setup from one to any number of lanes. Learn more...
Features Include:
-
Quick and reliable testing with our Signal Integrity Studio Software
-
Single and multi-channel JTOL measurements
-
Easy pattern template editor; no plotting required
-
A perfect fit for any budget
Characterizing Crosstalk
The PCB12500 Parallel Channel BERT is an ideal instrument for characterizing multichannel crosstalk with multiple aggressors. The PCB12500 controller supports up to 5 remote heads. We are using two different types of heads: TG5P1A Pattern Generator heads (with de-emphasis), and TR2P1A Error Detector heads. The PCB12500 controls each head and provides each with an independently-controlled phase-shifted clock. Learn more...
Features Include:
-
Multi-channel test system designed for high-density ICs and backplanes
-
Victim channel jitter characterization provides sensitivity analysis
-
Complex system configurations with many NeXT and FeXT aggressors
-
Asynchronous aggressors from one clock source (with PCB12500)
-
Single- and multi-tap de-emphasis, fully programmable generators
12.5 Gb/s Programmable Stressed Pattern Generation
The PPG12500 Programmable Pattern Generator offers full user programmable patterns up to 24 Mbit in length and integrated two tap de-emphasis signal conditioning. Combined with the SCS16000 Series of Stressed Clock Synthesizers as the clock source, the pair create the perfect stressed pattern generation system for electrical serial data applications. Learn more...
Features Include:
-
Affordable - no need to time share lab instruments
-
Full complement of built-in stress sources
-
User programmable patterns
-
Integrated de-emphasis
-
Outstanding eye shape fidelity
Affordable Multi-Lane BERT Solution
The PCB12500 Parallel Channel BERT and the SCS16000J Stressed Clock Synthesizer combine to form a compact, inexpensive solution for measuring BER on multi-lane systems. Learn more...
Features Include:
-
Modular Parallel BERT Solution
-
Remote Heads that Minimize Cable Loss
-
Multi-Channel JTOL
-
Integrated De-emphasis
XFP, SFP+, and QSFP Testing
The TG1B1-A 10G BERT provides accurate, repeatable BER measurements for a fraction of the cost of a competitive BERT. With an internal narrow range clock adjustable from 9.85 – 11.35 GHz, XFP, SFP+ and QSFP transceivers can be tested over a range of 10G data rates without the need for an external clock. Learn more...
Features Include:
-
Small footprint requires little bench space
-
Integrated 10 GHz clock source
-
Fully programmable for test flexibility
-
Affordable and reliable
Products
<10G: Solutions for Datacom Test Applications below 10Gbps
10G: Solutions for 10GbE, SONET OC-192, and other 10G Applications
40G: Test and Component Solutions for SONET OC-768 and 40GbE Applications
100G: 14G, 28G, and 56G Test and Component Solutions for 100GbE Applications